extractedLnx/linux-2.0.40/drivers/block/triton.c_ide_init_triton.c
void ide_init_triton (byte bus, byte fn)
{
byte bridgebus, bridgefn, bridgeset = 0, hpt34x_flag = 0;
unsigned char irq = 0;
int dma_enabled = 0, rc = 0, h;
unsigned short io[6], count = 0, step_count = 0, pass_count = 0;
unsigned short pcicmd, vendor, device, class;
unsigned int bmiba, timings, reg, tmp;
unsigned int addressbios = 0;
unsigned long flags;
unsigned index;
#if defined(DISPLAY_APOLLO_TIMINGS) || defined(DISPLAY_ALI15X3_TIMINGS)
bmide_bus = bus;
bmide_fn = fn;
#endif /* DISPLAY_APOLLO_TIMINGS || DISPLAY_ALI15X3_TIMINGS */
/*
* We pick up the vendor, device, and class info for selecting the correct
* controller that is supported. Since we can access this routine more than
* once with the use of onboard and off-board EIDE controllers, a method
* of determining "who is who for what" is needed.
*/
pcibios_read_config_word (bus, fn, PCI_VENDOR_ID, &vendor);
pcibios_read_config_word (bus, fn, PCI_DEVICE_ID, &device);
pcibios_read_config_word (bus, fn, PCI_CLASS_DEVICE, &class);
pcibios_read_config_byte (bus, fn, PCI_INTERRUPT_LINE, &irq);
switch(vendor) {
case PCI_VENDOR_ID_INTEL:
printk("ide: Intel 82371 ");
switch(device) {
case PCI_DEVICE_ID_INTEL_82371_0:
printk("PIIX (single FIFO) ");
break;
case PCI_DEVICE_ID_INTEL_82371SB_1:
printk("PIIX3 (dual FIFO) ");
break;
case PCI_DEVICE_ID_INTEL_82371AB:
printk("PIIX4 (dual FIFO) ");
break;
default:
printk(" (unknown) 0x%04x ", device);
break;
}
printk("DMA Bus Mastering IDE ");
break;
case PCI_VENDOR_ID_SI:
printk("ide: SiS 5513 (dual FIFO) DMA Bus Mastering IDE ");
break;
case PCI_VENDOR_ID_VIA:
printk("ide: VIA VT82C586B (split FIFO) UDMA Bus Mastering IDE ");
break;
case PCI_VENDOR_ID_TTI:
/*PCI_CLASS_STORAGE_UNKNOWN == class */
if (device == PCI_DEVICE_ID_TTI_HPT343) {
pcibios_write_config_byte(bus, fn, HPT343_PCI_INIT_REG, 0x00);
pcibios_read_config_word(bus, fn, PCI_COMMAND, &pcicmd);
hpt34x_flag = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
#if 1
if (!hpt34x_flag) {
save_flags(flags);
cli();
pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd & ~PCI_COMMAND_IO);
pcibios_read_config_dword(bus, fn, PCI_BASE_ADDRESS_4, &bmiba);
pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_0, bmiba | 0x20);
pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_1, bmiba | 0x34);
pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_2, bmiba | 0x28);
pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_3, bmiba | 0x3c);
pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd);
bmiba = 0;
restore_flags(flags);
}
#endif
pcibios_write_config_byte(bus, fn, PCI_LATENCY_TIMER, 0x20);
goto hpt343_jump_in;
} else {
printk("ide: HPTXXX did == 0x%04X unsupport chipset error.\n", device);
return;
}
case PCI_VENDOR_ID_PROMISE:
/*
* I have been able to make my Promise Ultra33 UDMA card change class.
* It has reported as both PCI_CLASS_STORAGE_RAID and PCI_CLASS_STORAGE_IDE.
* Since the PCI_CLASS_STORAGE_RAID mode should automatically mirror the
* two halves of the PCI_CONFIG register data, but sometimes it forgets.
* Thus we guarantee that they are identical, with a quick check and
* correction if needed.
* PDC20246 (primary) PDC20247 (secondary) IDE hwif's.
*
* PDC20262 Promise Ultra66 UDMA.
*
* Note that Promise "stories,fibs,..." about this device not being
* capable of ATAPI and AT devices.
*/
if (class != PCI_CLASS_STORAGE_IDE) {
unsigned char irq_mirror = 0;
pcibios_read_config_byte(bus, fn, (PCI_INTERRUPT_LINE)|0x80, &irq_mirror);
if (irq != irq_mirror) {
pcibios_write_config_byte(bus, fn, (PCI_INTERRUPT_LINE)|0x80, irq);
}
}
case PCI_VENDOR_ID_ARTOP:
/* PCI_CLASS_STORAGE_SCSI == class */
/*
* I have found that by stroking rom_enable_bit on both the AEC6210U/UF and
* PDC20246 controller cards, the features desired are almost guaranteed
* to be enabled and compatible. This ROM may not be registered in the
* config data, but it can be turned on. Registration failure has only
* been observed if and only if Linux sets up the pci_io_address in the
* 0x6000 range. If they are setup in the 0xef00 range it is reported.
* WHY??? got me.........
*/
hpt343_jump_in:
printk("ide: %s UDMA Bus Mastering ",
(device == PCI_DEVICE_ID_ARTOP_ATP850UF) ? "AEC6210" :
(device == PCI_DEVICE_ID_PROMISE_20246) ? "PDC20246" :
(device == PCI_DEVICE_ID_PROMISE_20262) ? "PDC20262" :
(hpt34x_flag && (device == PCI_DEVICE_ID_TTI_HPT343)) ? "HPT345" :
(device == PCI_DEVICE_ID_TTI_HPT343) ? "HPT343" : "UNKNOWN");
pcibios_read_config_dword(bus, fn, PCI_ROM_ADDRESS, &addressbios);
if (addressbios) {
pcibios_write_config_byte(bus, fn, PCI_ROM_ADDRESS, addressbios | PCI_ROM_ADDRESS_ENABLE);
printk("with ROM enabled at 0x%08x", addressbios);
}
/*
* This was stripped out of 2.1.XXX kernel code and parts from a patch called
* promise_update. This finds the PCI_BASE_ADDRESS spaces and makes them
* available for configuration later.
* PCI_BASE_ADDRESS_0 hwif0->io_base
* PCI_BASE_ADDRESS_1 hwif0->ctl_port
* PCI_BASE_ADDRESS_2 hwif1->io_base
* PCI_BASE_ADDRESS_3 hwif1->ctl_port
* PCI_BASE_ADDRESS_4 bmiba
*/
memset(io, 0, 6 * sizeof(unsigned short));
for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
pcibios_read_config_dword(bus, fn, reg, &tmp);
if (tmp & PCI_BASE_ADDRESS_SPACE_IO)
io[count++] = tmp & PCI_BASE_ADDRESS_IO_MASK;
}
break;
case PCI_VENDOR_ID_AL:
save_flags(flags);
cli();
for (index = 0; !pcibios_find_device (PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, index, &bridgebus, &bridgefn); ++index) {
bridgeset = setup_aladdin(bus, fn);
}
restore_flags(flags);
printk("ide: ALI15X3 (dual FIFO) DMA Bus Mastering IDE ");
break;
default:
return;
}
printk("\n Controller on PCI bus %d function %d\n", bus, fn);
/*
* See if IDE and BM-DMA features are enabled:
*/
if ((rc = pcibios_read_config_word(bus, fn, PCI_COMMAND, &pcicmd)))
goto quit;
if ((pcicmd & 1) == 0) {
printk("ide: ports are not enabled (BIOS)\n");
goto quit;
}
if ((pcicmd & 4) == 0) {
printk("ide: BM-DMA feature is not enabled (BIOS)\n");
} else {
/*
* Get the bmiba base address
*/
int try_again = 1;
do {
if ((rc = pcibios_read_config_dword(bus, fn, PCI_BASE_ADDRESS_4, &bmiba)))
goto quit;
bmiba &= 0xfff0; /* extract port base address */
if (bmiba) {
dma_enabled = 1;
break;
} else {
printk("ide: BM-DMA base register is invalid (0x%04x, PnP BIOS problem)\n", bmiba);
if (inb(((vendor == PCI_VENDOR_ID_AL) ? DEFAULT_BMALIBA :
(vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA :
DEFAULT_BMIBA)) != 0xff || !try_again)
break;
printk("ide: setting BM-DMA base register to 0x%04x\n",
((vendor == PCI_VENDOR_ID_AL) ? DEFAULT_BMALIBA :
(vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA :
DEFAULT_BMIBA));
if ((rc = pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd&~1)))
goto quit;
rc = pcibios_write_config_dword(bus, fn, 0x20,
((vendor == PCI_VENDOR_ID_AL) ? DEFAULT_BMALIBA :
(vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA :
DEFAULT_BMIBA)|1);
if (pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd|5) || rc)
goto quit;
}
} while (try_again--);
}
/*
* See if ide port(s) are enabled
*/
if ((rc = pcibios_read_config_dword(bus, fn,
(vendor == PCI_VENDOR_ID_PROMISE) ? 0x50 :
(vendor == PCI_VENDOR_ID_ARTOP) ? 0x54 :
(vendor == PCI_VENDOR_ID_SI) ? 0x48 :
(vendor == PCI_VENDOR_ID_AL) ? 0x08 :
0x40, &timings)))
goto quit;
/*
* We do a vendor check since the Ultra33/66 and AEC6210
* holds their timings in a different location.
*/
#if 0
printk("ide: timings == %08x\n", timings);
#endif
/*
* The switch preserves some stuff that was original.
*/
switch(vendor) {
case PCI_VENDOR_ID_INTEL:
if (!(timings & 0x80008000)) {
printk("ide: INTEL: neither port is enabled\n");
goto quit;
}
break;
case PCI_VENDOR_ID_VIA:
if(!(timings & 0x03)) {
printk("ide: VIA: neither port is enabled\n");
goto quit;
}
break;
case PCI_VENDOR_ID_AL:
timings <<= 16;
timings >>= 24;
if (!(timings & 0x30)) {
printk("ide: ALI15X3: neither port is enabled\n");
goto quit;
}
break;
case PCI_VENDOR_ID_SI:
timings <<= 8;
timings >>= 24;
if (!(timings & 0x06)) {
printk("ide: SIS5513: neither port is enabled\n");
goto quit;
}
break;
case PCI_VENDOR_ID_PROMISE:
printk(" (U)DMA Burst Bit %sABLED " \
"Primary %s Mode " \
"Secondary %s Mode.\n",
(inb(bmiba + 0x001f) & 1) ? "EN" : "DIS",
(inb(bmiba + 0x001a) & 1) ? "MASTER" : "PCI",
(inb(bmiba + 0x001b) & 1) ? "MASTER" : "PCI" );
#if 0
if (!(inb(bmiba + 0x001f) & 1)) {
outb(inb(bmiba + 0x001f)|0x01, (bmiba + 0x001f));
printk(" (U)DMA Burst Bit Forced %sABLED.\n",
(inb(bmiba + 0x001f) & 1) ? "EN" : "DIS");
}
#endif
break;
case PCI_VENDOR_ID_ARTOP:
case PCI_VENDOR_ID_TTI:
default:
break;
}
/*
* Save the dma_base port addr for each interface
*/
for (h = 0; h < MAX_HWIFS; ++h) {
ide_hwif_t *hwif = &ide_hwifs[h];
byte channel = ((h == 1) || (h == 3) || (h == 5)) ? 1 : 0;
/*
* This prevents the first contoller from accidentally
* initalizing the hwif's that it does not use and block
* an off-board ide-pci from getting in the game.
*/
if ((step_count >= 2) || (pass_count >= 2)) {
goto quit;
}
#if 0
if (hwif->chipset == ide_unknown)
printk("ide: index == %d channel(%d)\n", h, channel);
#endif
#ifdef CONFIG_BLK_DEV_OFFBOARD
/*
* This is a forced override for the onboard ide controller
* to be enabled, if one chooses to have an offboard ide-pci
* card as the primary booting device. This beasty is
* for offboard UDMA upgrades with hard disks, but saving
* the onboard DMA2 controllers for CDROMS, TAPES, ZIPS, etc...
*/
if (((vendor == PCI_VENDOR_ID_INTEL) ||
(vendor == PCI_VENDOR_ID_SI) ||
(vendor == PCI_VENDOR_ID_VIA) ||
(vendor == PCI_VENDOR_ID_AL)) && (h >= 2)) {
hwif->io_base = channel ? 0x170 : 0x1f0;
hwif->ctl_port = channel ? 0x376 : 0x3f6;
hwif->irq = channel ? 15 : 14;
hwif->noprobe = 0;
}
#endif /* CONFIG_BLK_DEV_OFFBOARD */
/*
* If the chipset is listed as "ide_unknown", lets get a
* hwif while they last. This does the first check on
* the current availability of the ide_hwifs[h] in question.
*/
if (hwif->chipset != ide_unknown) {
continue;
} else if (vendor == PCI_VENDOR_ID_INTEL) {
unsigned short time;
#ifdef DISPLAY_TRITON_TIMINGS
byte s_clks, r_clks;
unsigned short devid;
#endif /* DISPLAY_TRITON_TIMINGS */
pass_count++;
if (hwif->io_base == 0x1f0) {
time = timings & 0xffff;
if ((time & 0x8000) == 0) /* interface enabled? */
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba);
step_count++;
} else if (hwif->io_base == 0x170) {
time = timings >> 16;
if ((time & 0x8000) == 0) /* interface enabled? */
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba + 8);
step_count++;
} else {
continue;
}
#ifdef DISPLAY_TRITON_TIMINGS
s_clks = ((~time >> 12) & 3) + 2;
r_clks = ((~time >> 8) & 3) + 1;
printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d\n",
hwif->name, time, s_clks, r_clks);
if ((time & 0x40) && !pcibios_read_config_word(bus, fn, PCI_DEVICE_ID, &devid)
&& devid == PCI_DEVICE_ID_INTEL_82371SB_1) {
byte stime;
if (pcibios_read_config_byte(bus, fn, 0x44, &stime)) {
if (hwif->io_base == 0x1f0) {
s_clks = ~stime >> 6;
r_clks = ~stime >> 4;
} else {
s_clks = ~stime >> 2;
r_clks = ~stime;
}
s_clks = (s_clks & 3) + 2;
r_clks = (r_clks & 3) + 1;
printk(" slave: sample_CLKs=%d, recovery_CLKs=%d\n",
s_clks, r_clks);
}
}
print_triton_drive_flags (0, time & 0xf);
print_triton_drive_flags (1, (time >> 4) & 0xf);
#endif /* DISPLAY_TRITON_TIMINGS */
} else if (vendor == PCI_VENDOR_ID_SI) {
pass_count++;
if (hwif->io_base == 0x1f0) {
if ((timings & 0x02) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba);
step_count++;
} else if (hwif->io_base == 0x170) {
if ((timings & 0x04) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba + 8);
step_count++;
} else {
continue;
}
} else if (vendor == PCI_VENDOR_ID_VIA) {
pass_count++;
if (hwif->io_base == 0x1f0) {
if ((timings & 0x02) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba);
if (set_via_timings(bus, fn, 0xc0, 0xa0))
goto quit;
#ifdef DISPLAY_APOLLO_TIMINGS
proc_register_dynamic(&proc_root, &via_proc_entry);
#endif /* DISPLAY_APOLLO_TIMINGS */
step_count++;
} else if (hwif->io_base == 0x170) {
if ((timings & 0x01) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba + 8);
if (set_via_timings(bus, fn, 0x30, 0x50))
goto quit;
step_count++;
} else {
continue;
}
} else if (vendor == PCI_VENDOR_ID_AL) {
byte ideic, inmir;
byte irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
1, 11, 0, 12, 0, 14, 0, 15 };
if (bridgeset) {
pcibios_read_config_byte(bridgebus, bridgefn, 0x58, &ideic);
ideic = ideic & 0x03;
if ((channel && ideic == 0x03) || (!channel && !ideic)) {
pcibios_read_config_byte(bridgebus, bridgefn, 0x44, &inmir);
inmir = inmir & 0x0f;
hwif->irq = irq_routing_table[inmir];
} else if (channel && !(ideic & 0x01)) {
pcibios_read_config_byte(bridgebus, bridgefn, 0x75, &inmir);
inmir = inmir & 0x0f;
hwif->irq = irq_routing_table[inmir];
}
}
pass_count++;
if (hwif->io_base == 0x1f0) {
if ((timings & 0x20) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba);
outb(inb(bmiba+2) & 0x60, bmiba+2);
if (inb(bmiba+2) & 0x80)
printk("ALI15X3: simplex device: DMA forced\n");
#ifdef DISPLAY_ALI15X3_TIMINGS
proc_register_dynamic(&proc_root, &ali_proc_entry);
#endif /* DISPLAY_ALI15X3_TIMINGS */
step_count++;
} else if (hwif->io_base == 0x170) {
if ((timings & 0x10) == 0)
continue;
hwif->chipset = ide_triton;
if (dma_enabled)
init_triton_dma(hwif, bmiba + 8);
outb(inb(bmiba+10) & 0x60, bmiba+10);
if (inb(bmiba+10) & 0x80)
printk("ALI15X3: simplex device: DMA forced\n");
step_count++;
} else {
continue;
}
} else if ((vendor == PCI_VENDOR_ID_PROMISE) ||
(vendor == PCI_VENDOR_ID_ARTOP) ||
(vendor == PCI_VENDOR_ID_TTI)) {
pass_count++;
if (vendor == PCI_VENDOR_ID_TTI) {
if ((!hpt34x_flag) && (h < 2)) {
goto quit;
} else if (hpt34x_flag) {
hwif->io_base = channel ? (bmiba + 0x28) : (bmiba + 0x20);
hwif->ctl_port = channel ? (bmiba + 0x3e) : (bmiba + 0x36);
} else {
goto io_temps;
}
} else {
io_temps:
tmp = channel ? 2 : 0;
hwif->io_base = io[tmp];
hwif->ctl_port = io[tmp + 1] + 2;
}
hwif->irq = irq;
hwif->noprobe = 0;
if (device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
hwif->serialized = 1;
}
if ((vendor == PCI_VENDOR_ID_PROMISE) ||
(vendor == PCI_VENDOR_ID_TTI)) {
set_promise_hpt343_extra(device, bmiba);
}
if (dma_enabled) {
if ((!check_region(bmiba, 8)) && (!channel)) {
hwif->chipset = ((vendor == PCI_VENDOR_ID_TTI) && !hpt34x_flag) ? ide_hpt343 :
(device == PCI_DEVICE_ID_PROMISE_20262) ? ide_ultra66 : ide_udma;
init_triton_dma(hwif, bmiba);
step_count++;
} else if ((!check_region((bmiba + 0x08), 8)) && (channel)) {
hwif->chipset = ((vendor == PCI_VENDOR_ID_TTI) && !hpt34x_flag) ? ide_hpt343 :
(device == PCI_DEVICE_ID_PROMISE_20262) ? ide_ultra66 : ide_udma;
init_triton_dma(hwif, bmiba + 8);
step_count++;
} else {
continue;
}
}
}
}
quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
}
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