Binding Hardware Performance Counters

In order to use the hardware counters, we must add an architecture section to the configuration file, specifying the underlying hardware and binding Klogger's virtual counters to specific events supported by the hardware.

The basic structure is

arch ARCH_NAME {
        counter1 HARDWARE_COUNTER_NAME_A;
        counter2 HARDWARE_COUNTER_NAME_B;
	...
        counterN HARDWARE_COUNTER_NAME_X;
}

where ARCH_NAME is the architecture name (i.e. PentiumPro, PentiumIII, PentiumIV, etc.), ¹counter1...N are the virtual counter names, and HARDWARE_COUNTER_NAME_A...X are the hardware specific counter names. The list and descriptions of the hardware specific counter names supported for the given architecture can be viewed by running the command

./scripts/klogger-autogen.pl --list-counters

from the Klogger's kernel source root. For example, the counters currently supported for the PentiumIV architecture are listed in table 2.

Table 2: Hardware performance counters currently supported for the PentiumIV architecture. For full descriptions and the list of all counters supported by the hardware please refer to [5].

Counter Name	Counter Description
dtlb_miss	Page walks for a data TLB miss, all protection levels.
dtlb_miss_os	Page walks for a data TLB miss, OS protection level.
dtlb_miss_user	Page walks for a data TLB miss, user protection level.
itlb_miss	Page walks for an instruction TLB miss, all protection levels.
itlb_miss_os	Page walks for an instruction TLB miss, OS protection level.
itlb_miss_user	Page walks for an instruction TLB miss, user protection level.
l1_cache_misses	L1 cache misses, all protection levels.
l1_cache_misses_os	L1 cache misses, OS protection level.
l1_cache_misses_user	L1 cache misses, user protection level.
l2_cache_misses	L2 cache misses, all protection levels.
l2_cache_misses_os	L1 cache misses, OS protection level.
l2_cache_misses_user	L1 cache misses, user protection level.

Let's return to our SCHEDOUT example for a moment. Imagine we want Klogger to log not only the preempted process's pid, but also to log the number of overall L2 cache misses it has suffered.

Since we only want the event occurring when the process was running (regardless of any interrupts handled by the kernel during that time), we need to bind the first virtual counter to the underlying hardware's counter of the L2 cache misses occurring at the user protection level -- the l2_cache_misses_user counter. As such, the architecture dependant section in the configuration file would look like this:

arch PentiumIV {
        counter1 l2_cache_misses_user;
}

Also, we would add another 64bit integral field to the SCHEDOUT event, saving the counter's value at the moment of preemption:

event SCHEDOUT {
    int pid
    ulonglong l2_cache_misses_user
}

which means the textual log will hold the event as

{
    header => {
            "type"           => "SCHEDOUT",
            "serial"         => "119",
            "timestamp"      => "1032071755760",
    },
    "pid"                    => "1073",
    "l2_cache_misses_user"   => "35678014",
},

The next section describes how to read the hardware's performance counters, and how to log our extended SCHEDOUT event.