Yoav Etsion

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	Email: yetsion AT {tce,ee,cs}.technion.ac.il Address Technion Computer Engineering Center Technion - Israel Institute of Technology Technion City 32000 Haifa Israel
I am a Senior Lecturer (Assistant Professor) in the Electrical Engineering and Computer Science departments of the Technion - Israel Institute of Technology, and a memeber of the Technion Computer Engineering Center (TCE). Until recently, I was a Senior Researcher at the Barcelona Supercomputing Center (BSC). Before that, I completed my PhD at Hebrew University, under the supervision of Prof. Dror Feitelson. Obviously, I also have a CV (which I try to keep up-to-date...)

• FASPP Workshop
  I am a co-organizer of the 1st Workshop on Future Architectural Support for Parallel Programming (FASPP'11). Our goal is
  to bring together experts in computer architectures, parallel programming, parallel algorithms, and parallel system design, and foster a
  discussion on the design of future parallel architectures.
  The workshop will be held in conjunction with the 38th International Symposium on Computer Architecture (ISCA), on June 5, in San Jose, CA.
  
• PC Member
  Conferences: IPDPS (2012), HiPC (2010)
  Workshops: CAOS (2011, 2010), PMEA (2010)

• Klogger, A Linux Kernel Logging Framework.

• Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramirez, and Mateo Valero "On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels"
  In HiPEAC Conf., Jan 2012. (to appear)
  

2011

• Yoav Etsion and Dror G. Feitelson. "Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling"
  Accepted for publication in IEEE Transactions on Computers.
  

• Milan Pavlovic, Yoav Etsion, and Alex Ramirez. "On the Memory System Requirements of Future Scientific Applications: Four Case Studies"
  In IEEE Intl. Symp. on Workload Characterization (IISWC), Nov 2011.
  

• Carlos Villavieja, Vasilis Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal, Osman Unsal. "DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory"
  In Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Oct 2011.
  

• Carlos Villavieja, Yoav Etsion, Alex Ramirez, and Nacho Navarro. "FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores"
  In Euro-Par, Aug 2011.
  

• Alejandro Rico, Alex Duran, Felipe Cabarcas, Alex Ramirez, Yoav Etsion, and Mateo Valero. "Trace-driven Simulation of Multithreaded Applications"
  In Intl. Symp. Performance Analysis of Systems and Software (ISPASS), Apr 2011.
  

2010

• Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramirez, Rosa M. Badia, Eduard Ayguade, Jesus Labarta, and Mateo Valero, "Task Superscalar: An Out-of-Order Task Pipeline".
  In IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43), Dec 2010.
  

• Felipe Cabarcas, Alejandro Rico, Yoav Etsion, and Alex Ramirez, "Interleaving Granularity on High Bandwidth Memory Architecture for CMPs".
  In Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2010.
  

• Yoav Etsion, Alex Ramirez, Rosa M. Badia, Eduard Ayguade, Jesus Labarta, and Mateo Valero, "Task Superscalar: Using Processors as Functional Units".
  In USENIX Workshop on Hot Topics In Parallelism (HotPar), Jun 2010.
  

• Milan Pavlovic, Yoav Etsion, and Alex Ramirez, "Can Manycores Support the Memory Requirements of Scientific Applications?".
  In Workshop on Applications for Multi and Many Core Processors (A4MMC), Jun 2010.
  Awarded Best Paper

• Tal Ben-Nun, Yoav Etsion, and Dror G. Feitelson, "Design and Implementation of a Generic Resource Sharing Virtual Time Dispatcher".
  In SYSTOR, May 2010.
  

2009

• Yoav Etsion, Alex Ramirez, Rosa M. Badia, and Jesus Labarta, "Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline" (extended abstract).
  In Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Jul 2009. (56K)
  

• Yoav Etsion, Tal Ben-Nun, and Dror G. Feitelson, "A Global Scheduling Framework for Virtualization Environments" .
  In Workshop on System Management Techniques, Processes and Services (SMTPS), May 2009. (103K)
  Awarded Best Student Paper

2008

• Yoav Etsion, The Skewed Distribution of Working Sets: Leveraging Randomness for Cache Design .
  PhD Dissertation. Submitted to the Senate of the Hebrew University, Oct. 2008 (2.2M).

• Yoav Etsion and Dror G. Feitelson, Core Working Sets: Concept, Identification, and Use .
  Technical Report 2008-64, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Jul. 2008 (1.1M).

• Tal Ben-Nun, Yoav Etsion and Dror G. Feitelson, The Klogger Networking Schema .
  Technical Report 2008-1, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Jan. 2008 (40K).

2007

• Yoav Etsion and Dror G. Feitelson, "L1 Cache Filtering Through Random Selection of Memory References" .
  In Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 235-244, Sep 2007. (223K)

• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson, "Secretly monopolizing the CPU without superuser privileges" .
  In 16th USENIX Security Symposium, Aug 2007. (393K)

• Dror G. Feitelson, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Yoav Etsion, Gabor Madl, Esteban P. Osses, Sameer Singh, Karlkim Suwanmongkol, Charlie Xie, and Stephen R. Schach, "Fine-Grain Analysis of Common Coupling and its Application to a Linux Case Study" .
  In Journal of Systems and Software (JSS), 80(8), pp. 1239-1255, Aug 2007. (272K).

• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson, "Backfilling Using System-Generated Predictions Rather than User Runtime Estimates"
  In IEEE Transactions on Parallel and Distributed Systems (TPDS), 18(6), pp. 789-803, Jun 2007. (296K)
  

• Yoav Etsion and Dror G. Feitelson, "Probabilistic Prediction of Temporal Locality".
  In IEEE Computer Architecture Letters (CAL), 6(1), pp. 17-20, May 2007. (338K)
  

• Yoav Etsion, Dan Tsafrir, Scott Kirkpatrick, and Dror G. Feitelson, "Fine Grained Kernel Logging with KLogger: Experience and Insights" .
  In 2nd EuroSys, pp. 259-272, Mar 2007. (236K) Accompanied by the software itself.
  

2006

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson, "Process Prioritization Using Output Production: Scheduling for Multimedia".
  In ACM Trans. on Multimedia Computing, Communications, and Applications. (TOMCCAP), 2(4), pp. 318-342, Nov 2006. (350K)
  

• Eitan Frachtenberg and Yoav Etsion, Hardware Parallelism: Are Operating Systems Ready? (Case Studies in Mis-Scheduling) .
  In 2nd Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), pp. 7-15, Jun 2006. (362K)

2005

• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson, "Modeling User Runtime Estimates".
  In 11th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Jun 2005.
  D. G. Feitelson, E. Frachtenberg, L. Rudolph, and U. Schwiegelshohn (Eds.), pp. 1-35, Springer-Verlag, 2005. Lecture Notes in Computer Science Vol. 3834.
  

• Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, and Scott Kirkpatrick, "System Noise, OS Clock Ticks, and Fine-Grained Parallel Applications" .
  In the 19th Intl. Conf. on Supercomputing (ICS), pp. 303-312, Jun 2005. (204K)
  

• Dan Tsafrir, Yoav Etsion, and Dror G. Feitelson, "General Purpose Timing: The Failure of Periodic Timers".
  Technical Report 2005-6, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Feb. 2005 (137K).

2004

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson, "Desktop Scheduling: How Can We Know What the User Wants?".
  In the 14th ACM International Workshop on Network and Operating Systems Support for Digital Audio and Video (NOSSDAV), pp. 110-115, Jun 2004. (129 KB)
  

2003

• Yoav Etsion, Dan Tsafrir, and Dror G. Feitelson, "Effects of Clock Resolution on the Scheduling of Interactive and Soft Real-Time Processes".
  In the Intl. Conf. on Measurement & Modeling of Computer Systems (SIGMETRICS), pp. 172-183, Jun 2003. (297 KB)
  

2001

• Yoav Etsion and Dror G. Feitelson, "User-Level Communication in a System with Gang Scheduling".
  In the 15th Intl. Parallel and Distributed Processing Symp. (IPDPS), Apr 2001. (50 KB)
  Original extended version available as Technical Report 2000-39

1999

D. G. Feitelson, A. Batat, G. Benhanokh, D. Er-El, Y. Etsion, A. Kavas, T. Klainer, U. Lublin, and M. A. Volovic, The ParPar system: A software MPP.
In High Performance Cluster Computing, Vol 1: Architectures and Systems, Rajkumar Buyya (Ed.), pp. 754-770, Prentice-Hall, 1999. (108 KB)
Translated to Chinese.
• Yoav Etsion, Michael Raizman, and Dror G. Feitelson, Topology and Routing in Clusters: From Theory to Practice.
  Technical Report 99-??, School of Computer Science and Engineering, The Hebrew University of Jerusalem, Dec 1999 (266 KB).

• Virtutech Simics, the full system simulator (free for academic use)

• GEMS, multiprocessor simulator (based on Virtutech Simics)

• WWW Computer Architecture Page

• GNU C++ Book and Classes

• SGI's STL Documentation