//: version "1.8.5"

module main;    //: root_module
supply1 w7;    //: /sn:0 {0}(131,68)(131,134)(146,134){1}
//: {2}(148,132)(148,128)(157,128)(157,141){3}
//: {4}(148,136)(148,177)(144,177){5}
supply0 w0;    //: /sn:0 {0}(217,326)(217,287)(331,287)(331,309)(380,309)(380,283){1}
wire w6;    //: /sn:0 {0}(273,166)(283,166)(283,179)(177,179)(177,195){1}
//: {2}(175,197)(174,197)(174,187)(144,187){3}
//: {4}(177,199)(177,209){5}
wire [7:0] w14;    //: /sn:0 /dp:1 {0}(183,256)(369,256){1}
wire [7:0] w4;    //: /sn:0 {0}(516,208)(542,208)(542,254){1}
//: {2}(540,256)(404,256){3}
//: {4}(542,258)(542,263)(659,263){5}
wire w3;    //: /sn:0 {0}(224,106)(398,106)(398,172)(453,172){1}
//: {2}(457,172)(508,172)(508,203){3}
//: {4}(455,174)(455,200){5}
//: {6}(453,202)(387,202)(387,233){7}
//: {8}(455,204)(455,368)(469,368)(469,380)(616,380)(616,231)(667,231)(667,258){9}
wire w1;    //: /sn:0 /dp:1 {0}(259,397)(394,397)(394,283){1}
wire [7:0] w8;    //: /sn:0 /dp:1 {0}(675,263)(775,263)(775,237)(800,237)(800,41){1}
wire [7:0] w2;    //: /sn:0 {0}(105,193)(105,256)(167,256){1}
wire [7:0] w11;    //: /sn:0 {0}(33,51)(33,125)(105,125)(105,172){1}
wire w13;    //: /sn:0 {0}(-70,513)(-60,513)(-60,182)(68,182){1}
wire [7:0] w5;    //: /sn:0 /dp:1 {0}(500,208)(482,208)(482,80){1}
//: enddecls

  register MAR (.Q(w2), .D(w11), .EN(w6), .CLR(w7), .CK(w13));   //: @(105,182) /w:[ 0 1 3 5 1 ]
  //: joint g8 (w4) @(542, 256) /w:[ -1 1 2 4 ]
  bufif1 g4 (.Z(w4), .I(w5), .E(w3));   //: @(506,208) /sn:0 /w:[ 0 0 3 ]
  led RAMOutput (.I(w8));   //: @(800,34) /sn:0 /w:[ 1 ] /type:1
  //: supply0 g1 (w0) @(217,332) /sn:0 /w:[ 0 ]
  //: switch WriteNow (w3) @(207,106) /w:[ 0 ] /st:0
  //: supply1 g11 (w7) @(142,68) /sn:0 /w:[ 0 ]
  //: joint g16 (w6) @(177, 197) /w:[ -1 1 2 4 ]
  //: switch ReadNow (w1) @(242,397) /w:[ 0 ] /st:0
  //: joint g10 (w3) @(455, 172) /w:[ 2 -1 1 4 ]
  buf g19 (.I(w2), .Z(w14));   //: @(173,256) /sn:0 /w:[ 1 0 ]
  bufif0 g6 (.Z(w8), .I(w4), .E(w3));   //: @(665,263) /sn:0 /w:[ 0 5 9 ]
  //: joint g9 (w3) @(455, 202) /w:[ -1 5 6 8 ]
  ram MAINRAM (.A(w14), .D(w4), .WE(!w3), .OE(!w1), .CS(w0));   //: @(387,257) /w:[ 1 3 7 1 1 ]
  //: switch MAREnable (w6) @(256,166) /w:[ 0 ] /st:0
  //: joint g14 (w7) @(148, 134) /w:[ -1 2 1 4 ]
  //: dip MARInput (w11) @(33,41) /w:[ 0 ] /st:11
  //: dip RAMInput (w5) @(482,70) /w:[ 1 ] /st:180
  //: comment g0 /dolink:0 /link:"" @(163,540) /sn:0
  //: /line:"Note that there are inverters in the entrances of the RAM!. "
  //: /line:"The 2 tri-state devices are used to select between the input and the output of the circuit. "
  //: /line:""
  //: /line:"You must make sure that the write and the read swithces are not on \"on\" together. "
  //: /line:"In order to write , turn the switch on and then off (after a little while). "
  //: /line:"then, you can change address and do it again. "
  //: /line:""
  //: /line:"Dump the memory to file to see the results of what you wrote. "
  //: /line:""
  //: /line:"Note the buffer after the MAR (it is essential)."
  //: /line:""
  //: /line:"Yehuda. "
  //: /end
  clock g12 (.Z(w13));   //: @(-83,513) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50

endmodule