| Description |
Build the following gates, using solely elementary NAND gates, D-Flipflops (DFF) and previously-built gates:
The file should be submitted in their original directory structure:
- 1 - Bit, Register, RAM8, RAM64, PC.
- 2 - RAM512, RAM4K, RAM16K.
Each chip in this project is specified by a skeletal *.hdl program with a missing implementation part. In addition, each chip is accompanied by a supplied *.tst script file that tells the hardware simulator how to test it, and a supplied *.cmp file that lists the expected output of the *.hdl program, as mandated by the *.tst script file. All these files are available in a single zip file, which you should download to your computer (explained below).
The task: When loaded into the hardware simulator, your chip design (*.hdl program modified by you), tested on the script specified in the supplied *.tst file, should deliver the behavior specified in the supplied *.cmp file. If that is not the case, the simulator will let you know.
The Data Flip-Flop (DFF) gate is considered primitive and thus there is no need to build it: when the simulator encounters a DFF gate in an HDL program, it automatically invokes the built-in tools/builtIn/DFF.hdl implementation.
The directory structure of this project: When constructing RAM chips from smaller ones, we recommend using built-in versions of the latter. Otherwise, the simulator may run very slowly or even out of (real) memory space, since large RAM chips contain tens of thousands of lower level chips, and all these chips are kept in memory (as software objects) by the simulator. For this reason, we have placed the RAM512.hdl, RAM4K.hdl, and RAM16K.hdl programs in a separate directory. This way, the recursive descent construction of the RAM4K and RAM16K chips stops with the RAM512 chip, whereas the lower-level chips from which the latter chip is made are bound to be built-in (since the simulator does not find them in this directory).
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